ARM Cortex-A35 User Manual

B1.92 L2 Control Register
The L2CTLR characteristics are:
Purpose
Provides IMPLEMENTATION DEFINED control options for the L2 memory system.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
L2CTLR is writable. However, all writes to this register are ignored.
Configurations
L2CTLR is mapped to the AArch64 L2CTLR_EL1 register. See B2.74 L2 Control Register, EL1
on page B2-489.
There is one L2CTLR for the Cortex‑A35 processor.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
L2CTLR is a 32-bit register.
31 0
26 25 24
Reserved
Number of cores
RES0
23 1
L2 Data RAM input latency
22 21 20
Reserved
CPU Cache Protection
SCU- L2 Cache Protection
456
L2 Data RAM output latency
Reserved
Figure B1-46 L2CTLR bit assignments
[31:26]
Reserved, RES0.
Number of cores, [25:24]
Number of cores present:
0b00 One core, core 0.
0b01 Two cores, core 0 and core 1.
0b10 Three cores, cores 0 to 2.
0b11 Four cores, cores 0 to 3.
These bits are read-only and the value of this field is set to the number of cores present in the
configuration.
[23]
Reserved, RAZ.
CPU Cache Protection, [22]
CPU Cache Protection. Core RAMs are implemented:
0 Without ECC.
B1 AArch32 system registers
B1.92 L2 Control Register
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B1-303
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English