1 Double-bit errors are injected on all writes to the L2 cache data RAMs.
[28:25]
Reserved, RES0.
L2TEIEN, [24]
L2 cache tag RAM error injection enable. The possible values are:
0 Normal behavior, errors are not injected. This is the reset value.
1 Double-bit errors are injected on all writes to the L2 cache tag RAMs.
[23:15]
Reserved, RES0.
Enable UniqueClean evictions with data, [14]
Enables UniqueClean evictions with data. The possible values are:
0 Disables UniqueClean evictions with data. This is the reset value for ACE.
1 Enables UniqueClean evictions with data. This is the reset value for CHI.
In AXI implementations, this field is RES0.
[13:4]
Reserved, RES0.
Disable clean/evict push to external, [3]
Disables clean/evict push to external. The possible values are:
0 Enables clean/evict to be pushed out to external. This is the reset value for ACE.
1 Disables clean/evict from being pushed to external. This is the reset value for CHI.
In AXI implementations, this field is RES1.
[2:0]
Reserved, RES0.
To access the L2ACTLR:
MRC p15, 1, <Rt>, c15, c0, 0; Read L2ACTLR into Rt
MCR p15, 1, <Rt>, c15, c0, 0; Write Rt to L2ACTLR
Register access is encoded as follows:
Table B1-72 L2ACTLR access encoding
coproc opc1 CRn CRm opc2
1111 001 1111 0000 000
B1 AArch32 system registers
B1.91 L2 Auxiliary Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-302
Non-Confidential
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