ARM Cortex-A35 User Manual

B2.87 Reset Management Register, EL3
The RMR_EL3 characteristics are:
Purpose
Controls the execution state that the processor boots into and allows request of a warm reset.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
This register is subject to the CP15SDISABLE2 control, which prevents writing to this register
when the CP15SDISABLE2 signal is asserted.
Configurations
The RMR_EL3 is architecturally mapped to the AArch32 RMR register. See B1.103 Reset
Management Register on page B1-326.
Attributes
RMR_EL3 is a 32-bit register.
31
0
RES0
12
AA64
RR
Figure B2-58 RMR_EL3 bit assignments
[31:2]
Reserved, RES0.
RR, [1]
Reset Request. The possible values are:
0 This is the reset value.
1 Requests a warm reset. This bit is set to 0 by either a cold or warm reset.
The bit is strictly a request.
AA64, [0]
Determines which execution state the processor boots into after a warm reset. The possible
values are:
0 AArch32 Execution state.
1 AArch64 Execution state.
The reset vector address on reset takes a choice between two values, depending on the value in
the AA64 bit. This ensures that even with reprogramming of the AA64 bit, it is not possible to
change the reset vector to go to a different location.
The cold reset value depends on the AA64nAA32 signal.
B2 AArch64 system registers
B2.87 Reset Management Register, EL3
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B2-519
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English