ARM Cortex-A35 User Manual

B1.79 Instruction Set Attribute Register 5
The ID_ISAR5 characteristics are:
Purpose
Provides information about the instruction sets that the processor implements.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
ID_ISAR5 must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and
ID_ISAR4. See:
• B1.74 Instruction Set Attribute Register 0 on page B1-269
• B1.75 Instruction Set Attribute Register 1 on page B1-271
• B1.76 Instruction Set Attribute Register 2 on page B1-273
• B1.77 Instruction Set Attribute Register 3 on page B1-275
• B1.78 Instruction Set Attribute Register 4 on page B1-277
Configurations
ID_ISAR5 is architecturally mapped to AArch64 register ID_ISAR5_EL1. See B2.62 AArch32
Instruction Set Attribute Register 5, EL1 on page B2-465.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_ISAR5 is a 32-bit register.
31
12 11 8 7 0
RES0 SHA1 AES SEVLSHA2
4 316 1520 19
CRC32
Figure B1-34 ID_ISAR5 bit assignments
[31:20]
Reserved, RES0.
CRC32, [19:16]
Indicates whether CRC32 instructions are implemented in AArch32 state:
0x1 CRC32 instructions are implemented.
SHA2, [15:12]
Indicates whether SHA2 instructions are implemented in AArch32 state:
0x0 Cryptographic Extensions are not implemented or are disabled.
0x1 SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented.
See the Cortex
®
‑ A35 Processor Cryptographic Extension Technical Reference Manual for more
information.
SHA1, [11:8]
Indicates whether SHA1 instructions are implemented in AArch32 state:
B1 AArch32 system registers
B1.79 Instruction Set Attribute Register 5
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B1-279
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English