ARM Cortex-A35 User Manual

0x0 Cryptographic Extensions are not implemented or are disabled.
0x1 SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.
See the Cortex
®
‑ A35 Processor Cryptographic Extension Technical Reference Manual for more
information.
AES, [7:4]
Indicates whether AES instructions are implemented in AArch32 state:
0x0 Cryptographic Extensions are not implemented or are disabled.
0x2 AESE, AESD, AESMC and AESIMC, plus PMULL and PMULL2 instructions operating on 64-
bit data.
See the Cortex
®
‑ A35 Processor Cryptographic Extension Technical Reference Manual for more
information.
SEVL, [3:0]
Indicates whether the SEVL instruction is implemented:
0x1 SEVL implemented to send event local.
To access the ID_ISAR5:
MRC p15,0,<Rt>,c0,c2,5 ; Read ID_ISAR5 into Rt
Register access is encoded as follows:
Table B1-62 ID_ISAR5 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 101
B1 AArch32 system registers
B1.79 Instruction Set Attribute Register 5
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-280
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English