C10.12 Performance Monitors Peripheral Identification Register 0
The PMPIDR0 characteristics are:
Purpose
Provides information to identify a Performance Monitor component.
Usage constraints
The PMPIDR0 can be accessed through the external debug interface.
The accessibility to the PMPIDR0 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C2.2 External register access permissions to the PMU registers on page C2-587 describes the
condition codes.
Configurations
The PMPIDR0 is in the Debug power domain.
Attributes
See the register summary in C10.9 Memory-mapped PMU register summary on page C10-714.
RES0
31 0
78
Part_0
Figure C10-8 PMPIDR0 bit assignments
[31:8]
Reserved, RES0.
Part_0, [7:0]
0xDA Least significant byte of the performance monitor part number.
The PMPIDR0 can be accessed through the external debug interface, offset 0xFE0.
C10 PMU registers
C10.12 Performance Monitors Peripheral Identification Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-720
Non-Confidential
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