B1.76 Instruction Set Attribute Register 2
The ID_ISAR2 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See.
• B1.74 Instruction Set Attribute Register 0 on page B1-269
• B1.75 Instruction Set Attribute Register 1 on page B1-271
• B1.77 Instruction Set Attribute Register 3 on page B1-275
• B1.78 Instruction Set Attribute Register 4 on page B1-277
• B1.79 Instruction Set Attribute Register 5 on page B1-279
Configurations
ID_ISAR2 is architecturally mapped to AArch64 register ID_ISAR2_EL1. See B2.59 AArch32
Instruction Set Attribute Register 2, EL1 on page B2-459.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_ISAR2 is a 32-bit register.
31
28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
MultiAccessInt
Reversal PSR_AR MultU MultS Mult MemHint LoadStore
Figure B1-31 ID_ISAR2 bit assignments
Reversal, [31:28]
Indicates the implemented Reversal instructions:
0x2 The REV, REV16, and REVSH instructions.
The RBIT instruction.
PSR_AR, [27:24]
Indicates the implemented A and R profile instructions to manipulate the PSR:
0x1 The MRS and MSR instructions, and the exception return forms of data-processing
instructions.
The exception return forms of the data-processing instructions are:
• In the A32 instruction set, data-processing instructions with the PC as the destination and the
S bit set.
• In the T32 instruction set, the SUBS PC, LR, #N instruction.
MultU, [23:20]
Indicates the implemented advanced unsigned Multiply instructions:
B1 AArch32 system registers
B1.76 Instruction Set Attribute Register 2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-273
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