0x1 • The MOVT instruction.
• The MOV instruction encodings with zero-extended 16-bit immediates.
• The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates,
and other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for
those encodings.
IfThen, [19:16]
Indicates the implemented If-Then instructions in the T32 instruction set:
0x1 The IT instructions, and the IT bits in the PSRs.
Extend, [15:12]
Indicates the implemented Extend instructions:
0x2 • The SXTB, SXTH, UXTB, and UXTH instructions.
• The SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH
instructions.
Except_AR, [11:8]
Indicates the implemented A profile exception-handling instructions:
0x1 The SRS and RFE instructions, and the A profile forms of the CPS instruction.
Except, [7:4]
Indicates the implemented exception-handling instructions in the A32 instruction set:
0x1 The LDM (exception return), LDM (user registers), and STM (user registers) instruction
versions.
Endian, [3:0]
Indicates the implemented Endian instructions:
0x1 The SETEND instruction, and the E bit in the PSRs.
To access the ID_ISAR1:
MRC p15, 0, <Rt>, c0, c2, 1 ; Read ID_ISAR1 into Rt
Register access is encoded as follows:
Table B1-58 ID_ISAR1 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 001
B1 AArch32 system registers
B1.75 Instruction Set Attribute Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-272
Non-Confidential
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