B2.30 Cache Level ID Register, EL1
The CLIDR_EL1 characteristics are:
Purpose
Identifies:
• The type of cache, or caches, implemented at each level.
• The Level of Coherency and Level of Unification for the cache hierarchy.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
CLIDR_EL1 is architecturally mapped to AArch32 register CLIDR. See B1.40 Cache Level ID
Register on page B1-204.
Attributes
CLIDR_EL1 is a 64-bit register.
LoUIS RES0 Ctype3 Ctype2 Ctype1
32 30 29 27 26 24 23 21 20 9 8 6 5 3 2 0
LoUU LoC
ICB
Figure B2-5 CLIDR_EL1 bit assignments
[63:33]
Reserved, RES0.
ICB, [32:30]
Inner cache boundary. This field indicates the boundary between the inner and the outer domain.
0b000 Not disclosed in this mechanism.
LoUU, [29:27]
Indicates the Level of Unification Uniprocessor for the cache hierarchy:
0b001 L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or
invalidating to the point of unification for the processor.
LoC, [26:24]
Indicates the Level of Coherency for the cache hierarchy:
0b001 L2 cache not implemented. A clean to the point of coherency operation requires the L1
cache to be cleaned.
0b010 L2 cache implemented. A clean to the point of coherency operation requires the L1
and L2 caches to be cleaned.
LoUIS, [23:21]
Indicates the Level of Unification Inner Shareable for the cache hierarchy:
B2 AArch64 system registers
B2.30 Cache Level ID Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-400
Non-Confidential
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