NumSets, [27:13]
Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The
number of sets does not have to be a power of 2.
For more information about encoding, see Table B2-21 CCSIDR_EL1 encodings
on page B2-399.
Associativity, [12:3]
Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1.
The associativity does not have to be a power of 2.
For more information about encoding, see Table B2-21 CCSIDR_EL1 encodings
on page B2-399.
LineSize, [2:0]
Indicates the (log
2
(number of words in cache line)) - 2:
0b010 16 words per line.
The following table shows the individual bit field and complete register encodings for the CCSIDR_EL1.
Table B2-21 CCSIDR_EL1 encodings
CSSELR Cache Size Complete register
encoding
Register bit field encoding
WT WB RA WA NumSets Associativity LineSize
0x0
L1 Data cache 8KB
0x7003E01A
0 1 1 1
0x001F 0x003 0x2
16KB
0x7007E01A 0x003F 0x003 0x2
32KB
0x700FE01A 0x007F 0x003 0x2
64KB
0x701FE01A 0x00FF 0x003 0x2
0x1
L1 Instruction cache 8KB
0x2007E00A
0 0 1 0
0x003F 0x001 0x2
16KB
0x200FE00A 0x007F 0x001 0x2
32KB
0x201FE00A 0x00FF 0x001 0x2
64KB
0x203FE00A 0x001F 0x001 0x2
0x2
L2 cache 128KB
0x700FE03A
0 1 1 1
0x00FF 0x007 0x2
256KB
0x701FE03A 0x01FF 0x007 0x2
512KB
0x703FE03A 0x03FF 0x007 0x2
1024KB
0x707FE03A 0x07FF 0x007 0x2
0x3-0xF
Reserved - - - - - - - - -
To access the CCSIDR_EL1:
MRS <Xt>, CCSIDR_EL1 ; Read CCSIDR_EL1 into Xt
Register access is encoded as follows:
Table B2-22 CCSIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 0000 0000 000
B2 AArch64 system registers
B2.29 Cache Size ID Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-399
Non-Confidential
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