ARM Cortex-A35 User Manual

C8.6 External Debug Processor Feature Register
The EDPFR characteristics are:
Purpose
Provides additional information about implemented PE features in AArch64.
Usage constraints
This register is accessible as follows:
Default
RO
Configurations
The EDPFR is:
• Architecturally mapped to the AArch64 ID_AA64PFR0_EL1 register. See B2.54 AArch64
Processor Feature Register 0, EL1 on page B2-450.
• EDPFR is in the Debug power domain.
Attributes
EDPFR is a 64-bit register.
RES0
63 28
GIC
27 24
AdvSIMD
23 20
FP
19 16
EL3
15 12
EL2
11 8
EL1
7 4
EL0
3 0
Figure C8-5 EDPFR bit assignments
[63:28]
Reserved, RES0.
GIC, [27:24]
System register GIC interface. Defined values are:
0x0 No System register interface to the GIC is supported.
0x1 System register interface to the GIC CPU interface is supported.
All other values are reserved.
AdvSIMD, [23:20]
Advanced SIMD. Defined values are:
0x0 Advanced SIMD is implemented.
0xF Advanced SIMD is not implemented.
All other values are reserved.
FP, [19:16]
Floating-point. Defined values are:
0x0 Floating-point is implemented.
0xF Floating-point is not implemented.
All other values are reserved.
EL3 handling, [15:12]
C8 Memory-mapped debug registers
C8.6 External Debug Processor Feature Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-653
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English