B1.70 Hyp Translation Control Register
The HTCR characteristics are:
Purpose
Controls translation table walks required for the stage 1 translation of memory accesses from
Hyp mode, and holds cacheability and shareability information for the accesses.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
HTCR is architecturally mapped to AArch64 register TCR_EL2. See B2.95 Translation Control
Register, EL2 on page B2-540.
Attributes
HTCR is a 32-bit register.
8 712 1114 13 10 9
T0SZ
IRGN0
031
ORGN0
SH0RES0
3 230 24 23 22
RES0
RES1 RES1
RES0
Figure B1-26 HTCR bit assignments
[31]
Reserved, RES1.
[30:24]
Reserved, RES0.
[23]
Reserved, RES1.
[22:14]
Reserved, RES0.
SH0, [13:12]
Shareability attribute for memory associated with translation table walks using TTBR0. The
possible values are:
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer shareable.
0b11 Inner shareable.
ORGN0, [11:10]
Outer cacheability attribute for memory associated with translation table walks using TTBR0.
The possible values are:
0b00 Normal memory, Outer Non-cacheable.
B1 AArch32 system registers
B1.70 Hyp Translation Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-263
Non-Confidential
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