0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]
Inner cacheability attribute for memory associated with translation table walks using TTBR0.
The possible values are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:3]
Reserved, RES0.
T0SZ, [2:0]
Size offset of the memory region addressed by TTBR0. The region size is 2
(32-TSIZE)
bytes.
The processor does not use the implementation-defined bit, HTCR[30], so this bit is RES0.
To access the HTCR:
MRC p15, 4, <Rt>, c2, c0, 2; Read HTCR into Rt
MCR p15, 4, <Rt>, c2, c0, 2; Write Rt to HTCR
Register access is encoded as follows:
Table B1-54 HTCR access encoding
coproc opc1 CRn CRm opc2
1111 100 0010 0000 010
B1 AArch32 system registers
B1.70 Hyp Translation Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-264
Non-Confidential
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