C11.57 Device Affinity Register 0
The TRCDEVAFF0 characteristics are:
Purpose
Provides an additional core identification mechanism for scheduling purposes in a cluster.
TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
The TRCDEVAFF0 is:
• Architecturally mapped to the AArch64 MPIDR_EL1[31:0] register. See B2.83 Main ID
Register, EL1 on page B2-510.
• Architecturally mapped to external TRCDEVAFF0 register.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
TRCDEVAFF0 is a 32-bit register.
M
31 30 29 8 7 0
U Aff2 Aff0
25 24
MT
23
Aff1RES0
16 15
Figure C11-56 TRCDEVAFF0 bit assignments
M, [31]
Reserved, RES1.
U, [30]
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
0 Processor is part of a multiprocessor system. This is the value for implementations
with more than one core, and for implementations with an ACE or CHI master
interface.
1 Processor is part of a uniprocessor system. This is the value for single core
implementations with an AXI master interface.
[29:25]
Reserved, RES0.
MT, [24]
Indicates whether the lowest level of affinity consists of logical cores that are implemented
using a multi-threading type approach. This value is:
0 Performance of cores at the lowest affinity level is largely independent.
C11 ETM registers
C11.57 Device Affinity Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-804
Non-Confidential
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