B4.3 AArch64 Generic Timer register summary
The following table shows the AArch64 Generic Timer registers.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for information
about these registers.
Table B4-2 AArch64 Generic Timer registers
Name Op0 CRn Op1 CRm Op2 Reset Width Description
CNTKCTL_EL1 3 c14 0 c1 0 - 32-bit
Counter-timer Kernel Control register
The reset value for bits[9:8, 2:0] is 0b00000.
CNTFRQ_EL0 3 c0 0 UNK 32-bit
Counter-timer Frequency register
CNTPCT_EL0 1 UNK 64-bit
Counter-timer Physical Count register
CNTVCT_EL0 2 UNK 64-bit Counter-timer Virtual Count register
CNTP_TVAL_EL0 c2 0 UNK 32-bit
Counter-timer Physical Timer TimerValue register
CNTP_CTL_EL0 1
-
32-bit
Counter-timer Physical Timer Control register
The reset value for bit[0] is 0.
CNTP_CVAL_EL0 2 UNK 64-bit Counter-timer Physical Timer CompareValue register
CNTV_TVAL_EL0 c3 0 UNK 32-bit
Counter-timer Virtual Timer TimerValue register
CNTV_CTL_EL0 1 32-bit
Counter-timer Virtual Timer Control register
The reset value for bit[0] is 0.
CNTV_CVAL_EL0 2 UNK 64-bit Counter-timer Virtual Timer CompareValue register
CNTVOFF_EL2 4 c0 3 UNK 64-bit
Counter-timer Virtual Offset register
CNTHCTL_EL2 c1 0
-
32-bit
Counter-timer Hypervisor Control register
The reset value for bit[2] is 0 and for bits[1:0] is 0b11.
CNTHP_TVAL_EL2 c2 0 UNK 32-bit
Counter-timer Hypervisor Physical Timer TimerValue
register
CNTHP_CTL_EL2 1 32-bit
Counter-timer Hypervisor Physical Timer Control register
The reset value for bit[0] is 0.
CNTHP_CVAL_EL2 2 UNK 64-bit
Counter-timer Hypervisor Physical Timer CompareValue
register
CNTPS_TVAL_EL1 7 c2 0 UNK 32-bit
Counter-timer Physical Secure Timer TimerValue register
CNTPS_CTL_EL1 1 - 32-bit
Counter-timer Physical Secure Timer Control register
The reset value for bit[0] is 0.
CNTPS_CVAL_EL1 2 UNK 64-bit
Counter-timer Physical Secure Timer CompareValue
register
B4 Generic Timer registers
B4.3 AArch64 Generic Timer register summary
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