ARM Cortex-A35 User Manual

C10.1 AArch32 PMU register summary
The PMU counters and their associated control registers are accessible in the AArch32 Execution state
from the internal CP15 system register interface with MCR and MRC instructions for 32-bit registers and
MCRR and MRRC for 64-bit registers.
The following table gives a summary of the Cortex‑A35 PMU registers in the AArch32 Execution state.
For those registers not described in this chapter, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile.
See the C10.9 Memory-mapped PMU register summary on page C10-714 for a complete list of registers
that are accessible from the external debug interface.
Table C10-1 PMU register summary in the AArch32 Execution state
CRn Op1 CRm Op2 Name Type Width Description
c9 0 c12 0 PMCR RW 32 C10.2 Performance Monitors Control Register on page C10-692
c9 0 c12 1 PMCNTENSET RW 32
Performance Monitors Count Enable Set Register
c9 0 c12 2 PMCNTENCLR RW 32
Performance Monitors Count Enable Clear Register
c9 0 c12 3 PMOVSR RW 32 Performance Monitors Overflow Flag Status Register
c9 0 c12 4 PMSWINC WO 32
Performance Monitors Software Increment Register
c9 0 c12 5 PMSELR RW 32
Performance Monitors Event Counter Selection Register
c9 0 c12 6 PMCEID0 RO 32 C10.3 Performance Monitors Common Event Identification Register 0
on page C10-695
c9 0 c12 7 PMCEID1 RO 32 C10.4 Performance Monitors Common Event Identification Register 1
on page C10-699
c9 0 c13 0 PMCCNTR[31:0] RW 32
Performance Monitors Cycle Count Register
- 0 c9 - PMCCNTR[63:0] RW 64
c9 0 c13 1 PMXEVTYPER RW 32 Performance Monitors Selected Event Type Register
PMCCFILTR RW 32
Performance Monitors Cycle Count Filter Register
c9 0 c13 2 PMXEVCNTR RW 32 Performance Monitors Selected Event Count Register
c9 0 c14 0 PMUSERENR RW 32
Performance Monitors User Enable Register
c9 0 c14 1 PMINTENSET RW 32
Performance Monitors Interrupt Enable Set Register
c9 0 c14 2 PMINTENCLR RW 32
Performance Monitors Interrupt Enable Clear Register
c9 0 c14 3 PMOVSSET RW 32 Performance Monitor Overflow Flag Status Set Register
c14 0 c8 0 PMEVCNTR0 RW 32
Performance Monitor Event Count Registers
c14 0 c8 1 PMEVCNTR1 RW 32
c14 0 c8 2 PMEVCNTR2 RW 32
c14 0 c8 3 PMEVCNTR3 RW 32
c14 0 c8 4 PMEVCNTR4 RW 32
c14 0 c8 5 PMEVCNTR5 RW 32
C10 PMU registers
C10.1 AArch32 PMU register summary
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C10-690
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English