ARM Cortex-A35

Table C10-1 PMU register summary in the AArch32 Execution state (continued)
CRn Op1 CRm Op2 Name Type Width Description
c14 0 c12 0 PMEVTYPER0 RW 32
Performance Monitors Event Type Registers
c14 0 c12 1 PMEVTYPER1 RW 32
c14 0 c12 2 PMEVTYPER2 RW 32
c14 0 c12 3 PMEVTYPER3 RW 32
c14 0 c12 4 PMEVTYPER4 RW 32
c14 0 c12 5 PMEVTYPER5 RW 32
c14 0 c15 7 PMCCFILTR RW 32
Performance Monitors Cycle Count Filter Register
C10 PMU registers
C10.1 AArch32 PMU register summary
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C10-691
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