B2.8 AArch64 Address translation operations
The following table shows the address translation register in AArch64 state.
Table B2-7 AArch64 address translation register
Name Type Reset Width Description
PAR_EL1 RW UNK 64 B2.85 Physical Address Register, EL1 on page B2-514
The following table shows the System instructions for address translation operations in AArch64 state.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
Table B2-8 AArch64 address translation operations
Name Description
AT S1E1R
Stage 1 current state EL1 read
AT S1E1W
Stage 1 current state EL1 write
AT S1E0R
Stage 1 current state unprivileged read
AT S1E0W
Stage 1 current state unprivileged write
AT S1E2R
Stage 1 Hyp mode read
AT S1E2W
Stage 1 Hyp mode write
AT S12E1R
Stages 1 and 2 Non-secure EL1 read
AT S12E1W
Stages 1 and 2 Non-secure EL1 write
AT S12E0R
Stages 1 and 2 Non-secure unprivileged read
AT S12E0W
Stages 1 and 2 Non-secure unprivileged write
AT S1E3R
Stage 1 current state EL3 read
AT S1E3W
Stage 1 current state EL3 write
B2 AArch64 system registers
B2.8 AArch64 Address translation operations
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