ARM Cortex-A35 User Manual

B1.81 Memory Model Feature Register 1
The ID_MMFR1 characteristics are:
Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_MMFR0, ID_MMFR2, and ID_MMFR3. See:
• B1.80 Memory Model Feature Register 0 on page B1-281
• B1.82 Memory Model Feature Register 2 on page B1-285
• B1.83 Memory Model Feature Register 3 on page B1-287
Configurations
ID_MMFR1 is architecturally mapped to AArch64 register ID_MMFR1_EL1. See
B2.64 AArch32 Memory Model Feature Register 1, EL1 on page B2-469.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_MMFR1 is a 32-bit register.
31
12 11 8 7 0
BPred
4 328 27 2423 20 19 16 15
L1TstCln L1Uni L1Hvd L1UniSW L1HvdSW L1UniVA L1HvdVA
Figure B1-36 ID_MMFR1 bit assignments
BPred, [31:28]
Indicates branch predictor management requirements:
0x4 For execution correctness, branch predictor requires no flushing at any time.
L1TstCln, [27:24]
Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache
implementation:
0x0 None supported.
L1Uni, [23:20]
Indicates the supported entire L1 cache maintenance operations, for a unified cache
implementation:
0x0 None supported.
L1Hvd, [19:16]
Indicates the supported entire L1 cache maintenance operations, for a Harvard cache
implementation:
0x0 None supported.
B1 AArch32 system registers
B1.81 Memory Model Feature Register 1
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reserved.
B1-283
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English