ARM Cortex-A35 User Manual

L1UniSW, [15:12]
Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache
implementation:
0x0 None supported.
L1HvdSW, [11:8]
Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache
implementation:
0x0 None supported.
L1UniVA, [7:4]
Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache
implementation:
0x0 None supported.
L1HvdVA, [3:0]
Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache
implementation:
0x0 None supported.
To access the ID_MMFR1:
MRC p15, 0, <Rt>, c0, c1, 5; Read ID_MMFR1 into Rt
Register access is encoded as follows:
Table B1-64 ID_MMFR1 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 101
B1 AArch32 system registers
B1.81 Memory Model Feature Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-284
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English