ARM Cortex-A35 User Manual

B2.54 AArch64 Processor Feature Register 0, EL1
The ID_AA64PFR0_EL1 characteristics are:
Purpose
Provides additional information about implemented processor features in AArch64.
The optional Advanced SIMD and floating-point support is not included in the base product of
the processor. Arm requires licensees to have contractual rights to obtain the Advanced SIMD
and floating-point support.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_AA64PFR0_EL1 is architecturally mapped to external register EDPFR.
Attributes
ID_AA64PFR0_EL1 is a 64-bit register.
63 0
RES0
4 38 712 1116 15
EL3
handling
EL2
handling
EL1
handling
EL0
handling
FPAdvSIMD
20 1924 23
GIC
28 27
Figure B2-28 ID_AA64PFR0_EL1 bit assignments
[63:28]
Reserved, RES0.
GIC, [27:24]
GIC CPU interface:
0x0 GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x1 GIC CPU interface is implemented and enabled, GICCDISABLE is low.
AdvSIMD, [23:20]
Advanced SIMD. The possible values are:
0x0 Advanced SIMD is implemented.
0xF Advanced SIMD is not implemented.
The FP and AdvSIMD both take the same value, as both must be implemented, or neither.
FP, [19:16]
Floating-point. The possible values are:
0x0 Floating-point is implemented.
0xF Floating-point is not implemented.
The FP and AdvSIMD both take the same value, as both must be implemented, or neither.
EL3 handling, [15:12]
B2 AArch64 system registers
B2.54 AArch64 Processor Feature Register 0, EL1
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B2-450
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English