ARM Cortex-A35 User Manual

ASIDBits, [7:4]
Number of ASID bits:
0b0010 16 bits.
PARange, [3:0]
Physical address range supported:
0b0010 40 bits, 1TB.
To access the ID_AA64MMFR0_EL1:
MRS <Xt>, ID_AA64MMFR0_EL1 ; Read ID_AA64MMFR0_EL1 into Xt
Register access is encoded as follows:
Table B2-46 ID_AA64MMFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0111 000
B2 AArch64 system registers
B2.53 AArch64 Memory Model Feature Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-449
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English