ARM Cortex-A35 User Manual

A.12 ACE interface signals
The ACE protocol supports clock, configuration, and data handling signals when the processor uses this
protocol for the master memory interface.
This interface exists only if the Cortex‑A35 processor is configured to have the ACE interface.
All ACE channels must be balanced with respect to CLKIN and timed relative to ACLKENM.
Table A-24 ACE clock and configuration signals
Signal Direction Description
ACLKENM Input ACE Master bus clock enable.
ACINACTM Input
Snoop interface is inactive and not participating in coherency:
0
Snoop interface is active.
1
Snoop interface is inactive.
RDMEMATTR[7:0] Output Read request memory attributes.
WRMEMATTR[7:0] Output Write request memory attributes.
Table A-25 ACE write address channel signals
Signal Direction Description
AWADDRM[43:0] Output Write address.
AWBARM[1:0] Output Write barrier type.
AWBURSTM[1:0] Output
Write burst type.
AWCACHEM[3:0] Output
Write cache type.
AWDOMAINM[1:0] Output Write shareability domain type.
AWIDM[4:0] Output Write address ID.
AWLENM[7:0] Output
Write burst length.
AWLOCKM Output
Write lock type.
AWPROTM[2:0] Output
Write protection type.
AWREADYM Input
Write address ready.
AWSIZEM[2:0] Output
Write burst size.
AWSNOOPM[2:0] Output
Write snoop request type.
AWUNIQUEM Output
For WriteBack, WriteClean and WriteEvict transactions.
Indicates that the write is:
0
Shared.
1
Unique.
AWVALIDM Output
Write address valid.
A Signal Descriptions
A.12 ACE interface signals
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English