ARM Cortex-A35

Table A-26 ACE write data channel signals
Signal Direction Description
WDATAM[127:0] Output Write data
WIDM[4:0] Output Write data ID
WLASTM Output Write data last transfer indication
WREADYM Input Write data ready
WSTRBM[15:0] Output Write byte-lane strobes
WVALIDM Output Write data valid
Table A-27 ACE write data response channel signals
Signal Direction Description
BIDM[4:0] Input Write response ID
BREADYM Output Write response ready
BRESPM[1:0] Input Write response
BVALIDM Input Write response valid
Table A-28 ACE read address channel signals
Signal Direction Description
ARADDRM[43:0] Output
Read address.
The top 4 bits communicate only the ACE virtual address for DVM messages.
The top 4 bits are Read-as-Zero if a DVM message is not being broadcast.
ARBARM[1:0] Output Read barrier type.
ARBURSTM[1:0] Output
Read burst type.
ARCACHEM[3:0] Output
Read cache type.
ARDOMAINM[1:0] Output Read shareability domain type.
ARIDM[5:0] Output Read address ID.
ARLENM[7:0] Output
Read burst length.
ARLOCKM Output
Read lock type.
ARPROTM[2:0] Output
Read protection type.
ARREADYM Input
Read address ready.
ARSIZEM[2:0] Output
Read burst size.
ARSNOOPM[3:0] Output
Read snoop request type.
ARVALIDM Output
Read address valid.
A Signal Descriptions
A.12 ACE interface signals
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