B1.41 Architectural Feature Access Control Register
The CPACR characteristics are:
Purpose
Controls access to CP0 to CP13, and indicates which of CP0 to CP13 are implemented.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
The CPACR has no effect on instructions executed at EL2.
Configurations
CPACR is architecturally mapped to AArch64 register CPACR_EL1. See B2.31 Architectural
Feature Access Control Register, EL1 on page B2-402.
There is one copy of this register that is used in both Secure and Non-secure states.
Bits in the NSACR control Non-secure access to the CPACR fields. See the field descriptions
cp10 and cp11.
Attributes
CPACR is a 32-bit register.
31
24 23
22
21
20 19 0
RES0 cp11 cp10 RES0
30
ASEDIS
Figure B1-5 CPACR bit assignments
ASEDIS, [31]
Disable Advanced SIMD functionality:
0 Does not cause any instructions to be UNDEFINED. This is the reset value.
1 All instruction encodings that are part of Advanced SIMD, but that are not floating-point
instructions, are UNDEFINED.
If Advanced SIMD and floating-point are not implemented, this bit is RES0.
[30:24]
Reserved, RES0.
cp11, [23:22]
Defines the access rights for CP11, that control the Advanced SIMD and floating-point features.
Possible values of the fields are:
0b00 Access denied. Any attempt to access Advanced SIMD and floating-point registers or
instructions generates an Undefined Instruction exception. This is the reset value.
0b01 Access at EL1 only. Any attempt to access Advanced SIMD and floating-point registers
or instructions from software executing at EL0 generates an Undefined Instruction
exception.
0b10 Reserved.
B1 AArch32 system registers
B1.41 Architectural Feature Access Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-206
Non-Confidential
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