0b001 L2 cache not implemented or BROADCASTINNER set to 0.
The L1 cache is the last level of cache that must be cleaned or invalidated when
cleaning or invalidating to the point of unification for the Inner Shareable shareability
domain.
0b010 L2 cache implemented and BROADCASTINNER set to 1.
The L2 cache is the last level of cache that must be cleaned or invalidated when
cleaning or invalidating to the point of unification for the Inner Shareable shareability
domain.
[20:9]
Reserved, RES0.
Ctype3, [8:6]
Indicates the type of cache if the processor implements L3 cache:
0b000 L3 cache not implemented.
If software reads the Cache Type fields from Ctype1 upwards, after it has seen a value of 0b000,
no caches exist at further-out levels of the hierarchy. So, for example, if Ctype2 is the first
Cache Type field with a value of 0b000, the value of Ctype3 must be ignored.
Ctype2, [5:3]
Indicates the type of cache if the processor implements L2 cache:
0b000 L2 cache is not implemented.
0b100 L2 cache is implemented as a unified cache.
Ctype1, [2:0]
Indicates the type of cache implemented at L1:
0b011 Separate instruction and data caches at L1.
To access the CLIDR:
MRC p15,1,<Rt>,c0,c0,1 ; Read CLIDR into Rt
Register access is encoded as follows:
Table B1-34 CLIDR access encoding
coproc opc1 CRn CRm opc2
1111 001 0000 0000 001
B1 AArch32 system registers
B1.40 Cache Level ID Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-205
Non-Confidential
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