ARM Cortex-A35

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B1.109 TLB Type Register

TLBTR

The processor does not implement the features described by the TLBTR. This register is always RAZ.

B1 AArch32 system registers

B1.109 TLB Type Register

reserved.

B1-340

Non-Confidential

Main Page

Default Chapter5
- Table of Contents5
Preface19
- About this Book20
- Feedback25
Part a Functional Description27
- Chapter A129
Introduction29
- A1.1 about the Cortex ® -A35 Processor29
- A1.2 Features31
- A1.3 Implementation Options32
- Supported Standards and Specifications34
- A1.5 Test Features35
- A1.6 Design Tasks36
- A1.7 Product Revisions37
- Chapter A239
Technical Overview39
- A2.1 Components40
- A2.2 Interfaces44
- C4.1 about the Cross-Trigger45
- A2.3 about System Control46
- A2.4 about the Generic Timer47
- A2.5 about the Memory Model48
Chapter A349
Clocks, Resets, and Input Synchronization49
- A3.1 Clocks50
- A3.2 Input Synchronization51
- A3.3 Resets52
Chapter A457
Power Management57
- A4.1 Power Domains58
- A4.2 Power Modes61
- A4.3 Core Wait for Interrupt62
- A4.4 Core Wait for Event63
- A4.5 L2 Wait for Interrupt64
- A4.6 Powering down an Individual Core65
- A4.7 Powering up an Individual Core66
- A4.8 Powering down the Processor Without System Driven L2 Flush67
- A4.9 Powering up the Processor Without System Driven L2 Flush68
- A4.10 Powering down the Processor with System Driven L2 Flush69
- A4.11 Powering up the Processor with System Driven L2 Flush70
- A4.12 Entering Dormant Mode71
- A4.13 Exiting Dormant Mode72
- A4.14 Event Communication Using WFE or SEV73
- A4.15 Communication to the Power Management Controller74
- A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 Signals75
- A4.17 Q-Channel76
Chapter A577
- A5.1 Cached Memory Types78
- A5.2 Coherency between Data Caches with the MOESI Protocol79
- A5.3 Cache Misses, Unexpected Cache Hits, and Speculative Fetches80
- A5.4 Disabling a Cache81
- A5.5 Invalidating or Cleaning a Cache82
- A5.6 about Read Allocate Mode83
- A5.7 about Cache Protection84
- A5.8 Error Reporting86
- A5.9 Error Injection87
Cache Behavior and Cache Protection77
Chapter A689
L1 Memory System89
- A6.1 about the L1 Memory System90
- A6.2 TLB Organization91
- A6.3 Program Flow Prediction92
- A6.4 about the Internal Exclusive Monitor93
- A6.5 about Data Prefetching95
Chapter A797
L2 Memory System97
- A7.1 about the L2 Memory System98
- A7.2 Snoop and Maintenance Requests100
- A7.3 Support for Memory Types101
- A7.4 Memory Type Information Exported from the Processor102
- A7.5 Handling of External Aborts103
- Chapter A8105
AXI Master Interface105
- A8.1 about the AXI Master Interface106
- A8.2 AXI Privilege Information107
- A8.3 AXI Transactions108
- Attributes of the AXI Master Interface110
- Chapter A9113
ACE Master Interface113
- A9.1 about the ACE Master Interface114
- A9.2 ACE Configurations115
- A9.3 ACE Privilege Information116
- A9.4 ACE Transactions117
- Attributes of the ACE Master Interface120
- Snoop Channel Properties122
- A9.7 AXI Compatibility Mode123
- Chapter A10125
- Chapter A11135
ACP Slave Interface135
- A11.1 about the ACP136
- A11.2 Transfer Size Support137
- A11.3 ACP Performance138
- A11.4 ACP User Signals139
- Chapter A12141
GIC CPU Interface141
- A12.1 Bypassing the GIC CPU Interface142
- A12.2 Memory Map for the GIC CPU Interface143
Part B Register Descriptions145
- Chapter B1147
Aarch32 System Registers147
- B1.1 Aarch32 Register Summary150
- B1.2 C0 Registers152
- B1.3 C1 Registers155
- B1.4 C2 Registers156
- B1.5 C3 Registers157
- B1.6 C4 Registers158
- B1.7 C5 Registers159
- B1.8 C6 Registers160
- B1.9 C7 Registers161
- B1.10 C7 System Operations162
- B1.11 C8 System Operations165
- B1.12 C9 Registers167
- B1.13 C10 Registers168
- B1.14 C11 Registers169
- B1.15 C12 Registers170

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