C1.5 Debug events
A debug event can be either a software debug event or a halting debug event. A core responds to a debug
event in one of the following ways: ignores it, takes a debug exception, or enters debug state.
In the processor, watchpoint debug events are always synchronous. Memory hint instructions and cache
clean operations, except DC ZVA, DC IVAC, and DCIMVAC, do not generate watchpoint debug events.
Store exclusive instructions generate a watchpoint debug event even when the check for the control of
exclusive monitor fails. For watchpoint debug events, except those resulting from cache maintenance
operations, the value reported in DFAR is guaranteed to be no lower than the address of the watchpointed
location rounded down to a multiple of 16 bytes.
The powerup reset signal, nCPUPORESET, sets the Debug OS Lock. For the debug events and debug
register accesses to operate normally, the Debug OS Lock must be cleared.
Related information
A3.3 Resets on page A3-52
A.4 Reset signals on page Appx-A-851
Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile
C1 Debug
C1.5 Debug events
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C1-580
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