A11.1 About the ACP
The optional Accelerator Coherency Port (ACP) is implemented as an AXI4 slave interface with some
restrictions.
• 128-bit read and write interfaces.
• ARCACHE and AWCACHE are restricted to Normal, Write-Back, Read-Write-Allocate, Read-
Allocate, Write-Allocate, and No-Allocate memory. ARCACHE and AWCACHE are limited to the
values 0b0111, 0b1011, and 0b1111. Other values cause a SLVERR response on RRESP or BRESP.
• Exclusive accesses are not supported.
• Barriers are not supported. The BRESP handshake for a write transaction indicates global
observability for that write.
• ARSIZE and AWSIZE signals are not present and assume a value of 0b100, 16 bytes.
• ARBURST and AWBURST signals are not present and assume a value of INCR.
• ARLOCK and AWLOCK signals are not present.
• ARQOS and AWQOS signals are not present.
• ARLEN and AWLEN are limited to values 0 and 3.
A11 ACP Slave Interface
A11.1 About the ACP
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A11-136
Non-Confidential
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