B3.6 Virtual CPU interface register summary
The virtual CPU interface forwards virtual interrupts to a connected Cortex‑A35 processor, subject to the
normal GIC handling and prioritization rules.
The virtual interface control registers control virtual CPU interface operations. In particular, the virtual
CPU interface uses the contents of the List registers to determine when to signal virtual interrupts. When
a core accesses the virtual CPU interface, the List registers are updated. For more information on the
virtual CPU interface, see the Arm
®
Generic Interrupt Controller Architecture Specification.
The following table describes the registers for the virtual CPU interface.
All the registers in the following table are word-accessible. Registers not described in this table are RES0.
See the Arm
®
Generic Interrupt Controller Architecture Specification for more information.
Table B3-4 Virtual CPU interface register summary
Name Type Reset Description
GICV_CTLR RW
0x00000000
VM Control Register
GICV_PMR RW
0x00000000
VM Priority Mask Register
GICV_BPR RW
0x00000002
VM Binary Point Register
GICV_IAR RO - VM Interrupt Acknowledge Register
GICV_EOIR WO - VM End Of Interrupt Register
GICV_RPR RO
0x000000FF
VM Running Priority Register
GICV_HPPIR RO
0x000003FF
VM Highest Priority Pending Interrupt Register
GICV_ABPR RW
0x00000003
VM Aliased Binary Point Register
GICV_AIAR RO - VM Aliased Interrupt Acknowledge Register
GICV_AEOIR WO - VM Aliased End of Interrupt Register
GICV_AHPPIR RO
0x000003FF
VM Aliased Highest Priority Pending Interrupt Register
GICV_APR0 RW
0x00000000
B3.7 VM Active Priority Register on page B3-566
GICV_IIDR RO
0x0044343B
B3.8 VM CPU Interface Identification Register on page B3-567
GICV_DIR WO - VM Deactivate Interrupt Register
B3 GIC registers
B3.6 Virtual CPU interface register summary
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B3-565
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