B2.42 Exception Syndrome Register, EL2
The ESR_EL2 characteristics are:
Purpose
Holds syndrome information for an exception taken to EL2.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
ESR_EL2 is architecturally mapped to AArch32 register HSR. See B1.68 Hyp Syndrome
Register on page B1-258.
Attributes
ESR_EL2 is a 32-bit register.
ISS
31 26 25 24 0
EC
IL
Figure B2-17 ESR_EL2 bit assignments
EC, [31:26]
Exception Class. Indicates the reason for the exception that this register holds information
about.
IL, [25]
Instruction Length for synchronous exceptions. The possible values are:
0 16-bit.
1 32-bit.
ISS, [24:0]
Syndrome information.
When the EC field is 0x2F, indicating an SError interrupt has occurred, the ISS field contents are
IMPLEMENTATION DEFINED.
Table B2-34 ISS field contents for the Cortex-A35 processor
ISS[23:22] ISS[1:0] Description
0b00 0b00
DECERR on external access
0b00 0b01
Double-bit error detected on dirty line in L2 cache
0b00 0b10
SLVERR on external access
B2 AArch64 system registers
B2.42 Exception Syndrome Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-425
Non-Confidential
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