ARM Cortex-A35

Table B2-34 ISS field contents for the Cortex-A35 processor (continued)
ISS[23:22] ISS[1:0] Description
0b01 0b00
nSEI , or nVSEI in a guest OS, asserted
0b01 0b01
nREI asserted
To access the ESR_EL2:
MRS <Xt>, ESR_EL2 ; Read EL1 Exception Syndrome Register
MSR ESR_EL2, <Xt> ; Write EL1 Exception Syndrome Register
Register access is encoded as follows:
Table B2-35 ESR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 0101 0010 000
B2 AArch64 system registers
B2.42 Exception Syndrome Register, EL2
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