ARM Cortex-A35 User Manual

C11.14 ViewInst Main Control Register
The TRCVICTLR characteristics are:
Purpose
Controls instruction trace filtering.
Usage constraints
• Accepts writes only when the trace unit is disabled.
• Returns stable data only when TRCSTATR.PMSTABLE==1.
• Must be programmed, particularly to set the value of the SSSTATUS bit, that sets the state of
the start-stop logic.
Configurations
Available in all configurations.
Attributes
See C11.1 ETM register summary on page C11-733.
31 0
RES0
789101115 121619202324
RES0
SSSTATUS
TRCRESET
TRCERR
EXLEVEL_S
EXLEVEL_NS
RES0
6 34
SEL
TYPE
RES0
Figure C11-13 TRCVICTLR bit assignments
[31:24]
Reserved, RES0.
EXLEVEL_NS, [23:20]
In Non-secure state, each bit controls whether instruction tracing is enabled for the
corresponding exception level:
0 Trace unit generates instruction trace, in Non-secure state, for exception level n.
1 Trace unit does not generate instruction trace, in Non-secure state, for exception level
n.
The exception levels are:
Bit[20] Exception level 0.
Bit[21] Exception level 1.
Bit[22] Exception level 2.
Bit[23] RAZ/WI. Instruction tracing is not implemented for exception level 3.
EXLEVEL_S, [19:16]
In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
exception level:
0 Trace unit generates instruction trace, in Secure state, for exception level n.
1 Trace unit does not generate instruction trace, in Secure state, for exception level n.
The exception levels are:
Bit[16] Exception level 0.
C11 ETM registers
C11.14 ViewInst Main Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English