ARM Cortex-A35 User Manual

B2.83 Main ID Register, EL1
The MIDR_EL1 characteristics are:
Purpose
Provides identification information for the processor, including an implementer code for the
device and a device ID number.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The MIDR_EL1 is:
• Architecturally mapped to the AArch32 MIDR register. See B1.96 Main ID Register
on page B1-313.
• Architecturally mapped to external MIDR_EL1 register.
Attributes
MIDR_EL1 is a 32-bit register.
VariantImplementer
31 23 20 19 16 15 4 3 0
Architecture PartNum Revision
24
Figure B2-53 MIDR_EL1 bit assignments
Implementer, [31:24]
Indicates the implementer code. This value is:
0x41 ASCII character 'A' - implementer is Arm.
Variant, [23:20]
Indicates the variant number of the processor. This is the major revision number x in the rx part
of the rxpy description of the product revision status. This value is:
0x1 r1p0.
Architecture, [19:16]
Indicates the architecture code. This value is:
0xF Defined by CPUID scheme.
PartNum, [15:4]
Indicates the primary part number. This value is:
0xD04 Cortex‑A35 processor.
Revision, [3:0]
Indicates the minor revision number of the processor. This is the minor revision number y in the
py part of the rxpy description of the product revision status. This value is:
0x0 r1p0.
B2 AArch64 system registers
B2.83 Main ID Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-510
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English