ARM Cortex-A35

To access the MIDR_EL1:
MRS <Xt>, MIDR_EL1 ; Read MIDR_EL1 into Xt
Table B2-77 MIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0000 000
The MIDR_EL1 can be accessed through the external debug interface, offset 0xD00.
B2 AArch64 system registers
B2.83 Main ID Register, EL1
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B2-511
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