B2.12 AArch64 Secure registers
The following table shows the secure registers in AArch64 state.
Table B2-12 AArch64 security registers
Name Type Reset Width Description
SCR_EL3 RW
0x00000000
32 B2.89 Secure Configuration Register, EL3 on page B2-522
SDER32_EL3 RW
0x00000000
32 B2.93 Secure Debug Enable Register, EL3 on page B2-535
CPTR_EL3 RW
0x00000000
32
B2.33 Architectural Feature Trap Register, EL3 on page B2-406
Reset value is 0x00000000 if Advanced SIMD and floating- point are implemented,
0x00000400 otherwise.
MDCR_EL3 RW
0x00000000
32 B2.81 Monitor Debug Configuration Register, EL3 on page B2-503
AFSR0_EL3 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
AFSR1_EL3 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
VBAR_EL3 RW UNK 64 B2.102 Vector Base Address Register, EL3 on page B2-553
B2 AArch64 system registers
B2.12 AArch64 Secure registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-376
Non-Confidential
To Next Page
Loading...
