ARM Cortex-A35 User Manual

B1.63 Hyp Debug Control Register
The HDCR characteristics are:
Purpose
Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions
provided by the debug and trace architectures and the Performance Monitor.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
HDCR is architecturally mapped to AArch64 register MDCR_EL2. See B2.80 Monitor Debug
Configuration Register, EL2 on page B2-500.
This register is accessible only at EL2 or EL3.
Attributes
HDCR is a 32-bit register.
31 11 10 9 8 7 6 5 4 0
RES0 HPMN
TDOSA
TDA
TDE
HPME
TPM
TPMCR
12
TDRA
Figure B1-19 HDCR bit assignments
[31:12]
Reserved, RES0.
TDRA, [11]
Trap debug ROM address register access.
0 Has no effect on accesses to debug ROM address registers from EL1 and EL0.
1 Trap valid Non-secure EL1 and EL0 access to debug ROM address registers to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the following registers is trapped to
Hyp mode:
• DBGDRAR.
• DBGDSAR.
If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other
than for the value read back from HDCR.
On Warm reset, the field resets to 0.
TDOSA, [10]
Trap Debug OS-related register access:
B1 AArch32 system registers
B1.63 Hyp Debug Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-248
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English