A5.3 Cache misses, unexpected cache hits, and speculative fetches
The L1 and L2 caches handle problematic cache accesses in predefined ways.
Cache miss
On a cache miss, the processor performs Critical Word First filling of the cache.
Unexpected cache hits
If the cache reports a hit on a memory location that is marked as Non-Cacheable or Device, this is called
an unexpected cache hit. In this architecturally UNPREDICTABLE case, the cache might return incorrect data
because of the following configurations or settings:
• Improper translation table configuration because the caches are physically addressed.
• The cache is disabled.
Non-Cacheable or Device accesses do not use the result of a cache lookup and therefore ignore any
unexpected cache hit.
Speculative fetches
Because there can be several unresolved branches in the pipeline, there is no guarantee that the processor
executes an instruction. Instruction fetches are therefore speculative. A branch or exceptional instruction
in the code stream can cause a pipeline flush and discard the fetched instructions. Because of the
prefetching behavior, you must not place read-sensitive devices in the same page as code. Pages with
Device memory type attributes are treated as Non-Cacheable Normal Memory when accessed by
instruction fetches. You must use the XN (Execute Never) bit in the page table descriptor for a memory
region to stop speculative instructions fetches when such memory region contains read-sensitive devices.
To avoid speculative fetches to read-sensitive devices when address translation is disabled, these devices
must be separated from code in the physical memory map.
Related information
Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile
A5 Cache Behavior and Cache Protection
A5.3 Cache misses, unexpected cache hits, and speculative fetches
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A5-80
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