ARM Cortex-A35 User Manual

B1.55 Hyp Auxiliary Control Register
The HACTLR characteristics are:
Purpose
Controls write access to IMPLEMENTATION DEFINED registers in Non-secure EL1 modes, such as
CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR, and L2ACTLR.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
The HACTLR is architecturally mapped to the AArch64 ACTLR_EL2 register. See
B2.20 Auxiliary Control Register, EL2 on page B2-387.
Attributes
HACTLR is a 32-bit register.
31
0
RES0
L2ACTLR access control
1234567
L2ECTLR access control
L2CTLR access control
RES0
CPUECTLR access control
CPUACTLR access control
Figure B1-15 HACTLR bit assignments
[31:7]
Reserved, RES0.
L2ACTLR access control, [6]
L2ACTLR write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.
This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR(S)[6] to be set.
L2ECTLR access control, [5]
L2ECTLR write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.
This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR(S)[5] to be set.
B1 AArch32 system registers
B1.55 Hyp Auxiliary Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-231
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English