L2CTLR access control, [4]
L2CTLR write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.
This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR(S)[4] to be set.
[3:2]
Reserved, RES0.
CPUECTLR access control, [1]
CPUECTLR write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.
This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR(S)[1] to be set.
CPUACTLR access control, [0]
CPUACTLR write access control. The possible values are:
0 The register is not write accessible from Non-secure EL1.
This is the reset value.
1 The register is write accessible from Non-secure EL1.
Write access from Non-secure EL1 also requires ACTLR(S)[0] to be set.
To access the HACTLR:
MRC p15,4,<Rt>,c1,c0,1 ; Read HACTLR into Rt
MCR p15,4,<Rt>,c1,c0,1 ; Write Rt to HACTLR
Register access is encoded as follows:
Table B1-44 HACTLR access encoding
coproc opc1 CRn CRm opc2
1111 100 0001 0000 001
B1 AArch32 system registers
B1.55 Hyp Auxiliary Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-232
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