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ARM Cortex-A35

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B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3
AFSR0_EL1, AFSR0_EL2, and AFSR0_EL3
The processor does not implement AFSR0_EL1, AFSR0_EL2, and AFSR0_EL3. These registers are
always RES0.
B2 AArch64 system registers
B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-391
Non-Confidential

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