CPUECTLR_EL1 access control, [1]
CPUECTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
CPUACTLR_EL1 access control, [0]
CPUACTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
To access the ACTLR_EL3:
MRS <Xt>, ACTLR_EL3 ; Read ACTLR_EL3 into Xt
MSR ACTLR_EL3, <Xt> ; Write Xt to ACTLR_EL3
Register access is encoded as follows:
Table B2-19 ACTLR_EL3 access encoding
op0 op1 CRn CRm op2
11 110 0001 0000 001
B2 AArch64 system registers
B2.21 Auxiliary Control Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-390
Non-Confidential
To Next Page
Loading...
