ARM Cortex-A35 User Manual

B1.11 c8 system operations
System operations are divided into two categories. When the CRn value is c8, these operations are called
c8 system operations.
The following table shows the System operations when CRn is c8 and the processor is in AArch32 state.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information about these operations.
Table B1-11 c8 System operations summary
op1 CRm op2 Name Description
0 c3 0
TLBIALLIS
Invalidate entire TLB Inner Shareable
1
TLBIMVAIS
Invalidate unified TLB entry by VA and ASID Inner Shareable
2
TLBIASIDIS
Invalidate unified TLB by ASID match Inner Shareable
3
TLBIMVAAIS
Invalidate unified TLB entry by VA all ASID Inner Shareable
5
TLBIMVALIS
Invalidate unified TLB entry by VA Inner Shareable, Last level
7
TLBIMVAALIS
Invalidate unified TLB by VA all ASID Inner Shareable, Last level
c5 0
ITLBIALL
Invalidate instruction TLB
1
ITLBIMVA
Invalidate instruction TLB entry by VA and ASID
2
ITLBIASID
Invalidate instruction TLB by ASID match
c6 0
DTLBIALL
Invalidate data TLB
1
DTLBIMVA
Invalidate data TLB entry by VA and ASID
2
DTLBIASID
Invalidate data TLB by ASID match
c7 0
TLBIALL
Invalidate unified TLB
1
TLBIMVA
Invalidate unified TLB by VA and ASID
2
TLBIASID
Invalidate unified TLB by ASID match
3
TLBIMVAA
Invalidate unified TLB entries by VA all ASID
5
TLBIMVAL
Invalidate last level of stage 1 TLB entry by VA
7
TLBIMVAAL
Invalidate last level of stage 1 TLB entry by VA all ASID
B1 AArch32 system registers
B1.11 c8 system operations
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English