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T
able B1-10 c7 System operation summary (continued)
op1
CRm
op2
Name
Description
4
c8
0
ATS1HR
Stage 1 Hyp mode read
1
ATS1HW
Stage 1 Hyp mode write
B1 AArch32 system registers
B1.10 c7 system operations
100236_0100_00_en
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-164
Non-Confidential
163
165
Table of Contents
Default Chapter
5
Table of Contents
5
Preface
19
About this Book
20
Feedback
25
Part a Functional Description
27
Chapter A1
29
Introduction
29
A1.1 about the Cortex ® -A35 Processor
29
A1.2 Features
31
A1.3 Implementation Options
32
Supported Standards and Specifications
34
A1.5 Test Features
35
A1.6 Design Tasks
36
A1.7 Product Revisions
37
Chapter A2
39
Technical Overview
39
A2.1 Components
40
A2.2 Interfaces
44
C4.1 about the Cross-Trigger
45
A2.3 about System Control
46
A2.4 about the Generic Timer
47
A2.5 about the Memory Model
48
Chapter A3
49
Clocks, Resets, and Input Synchronization
49
A3.1 Clocks
50
A3.2 Input Synchronization
51
A3.3 Resets
52
Chapter A4
57
Power Management
57
A4.1 Power Domains
58
A4.2 Power Modes
61
A4.3 Core Wait for Interrupt
62
A4.4 Core Wait for Event
63
A4.5 L2 Wait for Interrupt
64
A4.6 Powering down an Individual Core
65
A4.7 Powering up an Individual Core
66
A4.8 Powering down the Processor Without System Driven L2 Flush
67
A4.9 Powering up the Processor Without System Driven L2 Flush
68
A4.10 Powering down the Processor with System Driven L2 Flush
69
A4.11 Powering up the Processor with System Driven L2 Flush
70
A4.12 Entering Dormant Mode
71
A4.13 Exiting Dormant Mode
72
A4.14 Event Communication Using WFE or SEV
73
A4.15 Communication to the Power Management Controller
74
A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 Signals
75
A4.17 Q-Channel
76
Chapter A5
77
A5.1 Cached Memory Types
78
A5.2 Coherency between Data Caches with the MOESI Protocol
79
A5.3 Cache Misses, Unexpected Cache Hits, and Speculative Fetches
80
A5.4 Disabling a Cache
81
A5.5 Invalidating or Cleaning a Cache
82
A5.6 about Read Allocate Mode
83
A5.7 about Cache Protection
84
A5.8 Error Reporting
86
A5.9 Error Injection
87
Cache Behavior and Cache Protection
77
Chapter A6
89
L1 Memory System
89
A6.1 about the L1 Memory System
90
A6.2 TLB Organization
91
A6.3 Program Flow Prediction
92
A6.4 about the Internal Exclusive Monitor
93
A6.5 about Data Prefetching
95
Chapter A7
97
L2 Memory System
97
A7.1 about the L2 Memory System
98
A7.2 Snoop and Maintenance Requests
100
A7.3 Support for Memory Types
101
A7.4 Memory Type Information Exported from the Processor
102
A7.5 Handling of External Aborts
103
Chapter A8
105
AXI Master Interface
105
A8.1 about the AXI Master Interface
106
A8.2 AXI Privilege Information
107
A8.3 AXI Transactions
108
Attributes of the AXI Master Interface
110
Chapter A9
113
ACE Master Interface
113
A9.1 about the ACE Master Interface
114
A9.2 ACE Configurations
115
A9.3 ACE Privilege Information
116
A9.4 ACE Transactions
117
Attributes of the ACE Master Interface
120
Snoop Channel Properties
122
A9.7 AXI Compatibility Mode
123
Chapter A10
125
A10.1 about the CHI Master Interface
126
A10.2 CHI Configurations
127
A10.3 Attributes of the CHI Master Interface
128
A10.4 CHI Channel Properties
130
A10.5 CHI Transactions
131
Chapter A11
135
ACP Slave Interface
135
A11.1 about the ACP
136
A11.2 Transfer Size Support
137
A11.3 ACP Performance
138
A11.4 ACP User Signals
139
Chapter A12
141
GIC CPU Interface
141
A12.1 Bypassing the GIC CPU Interface
142
A12.2 Memory Map for the GIC CPU Interface
143
Part B Register Descriptions
145
Chapter B1
147
Aarch32 System Registers
147
B1.1 Aarch32 Register Summary
150
B1.2 C0 Registers
152
B1.3 C1 Registers
155
B1.4 C2 Registers
156
B1.5 C3 Registers
157
B1.6 C4 Registers
158
B1.7 C5 Registers
159
B1.8 C6 Registers
160
B1.9 C7 Registers
161
B1.10 C7 System Operations
162
B1.11 C8 System Operations
165
B1.12 C9 Registers
167
B1.13 C10 Registers
168
B1.14 C11 Registers
169
B1.15 C12 Registers
170
B1.16 C13 Registers
172
B1.17 C14 Registers
173
B1.18 C15 Registers
174
B1.19 64-Bit Registers
175
B1.20 Aarch32 Identification Registers
176
B1.21 Aarch32 Virtual Memory Control Registers
178
B1.22 Aarch32 Fault Handling Registers
179
B1.23 Aarch32 Other System Control Registers
180
B1.24 Aarch32 Address Registers
181
B1.25 Aarch32 Thread Registers
182
B1.26 Aarch32 Performance Monitor Registers
183
B1.27 Aarch32 Secure Registers
185
B1.28 Aarch32 Virtualization Registers
186
B1.29 Aarch32 GIC System Registers
188
B1.30 Aarch32 Generic Timer Registers
190
B1.31 Aarch32 Implementation Defined Registers
191
B1.32 Auxiliary Control Register
193
B1.33 Auxiliary Data Fault Status Register
195
B1.34 Auxiliary ID Register
196
B1.35 Auxiliary Instruction Fault Status Register
197
B1.36 Auxiliary Memory Attribute Indirection Register 0
198
B1.37 Auxiliary Memory Attribute Indirection Register 1
199
B1.38 Configuration Base Address Register
200
B1.39 Cache Size ID Register
201
B1.40 Cache Level ID Register
204
B1.41 Architectural Feature Access Control Register
206
B1.42 CPU Auxiliary Control Register
208
B1.43 CPU Extended Control Register
212
B1.44 CPU Memory Error Syndrome Register
214
B1.45 Cache Size Selection Register
217
B1.46 Cache Type Register
219
B1.47 Domain Access Control Register
221
B1.48 Data Fault Address Register
222
B1.49 Data Fault Status Register
223
B1.50 DFSR with Short-Descriptor Translation Table Format
224
B1.51 DFSR with Long-Descriptor Translation Table Format
226
B1.52 Encoding of ISS[24:20] When HSR[31:30] Is 0B00
228
B1.53 FCSE Process ID Register
229
B1.54 Hyp Auxiliary Configuration Register
230
B1.55 Hyp Auxiliary Control Register
231
B1.56 Hyp Auxiliary Data Fault Status Syndrome Register
233
B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register
234
B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0
235
B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1
236
B1.60 Hyp Architectural Feature Trap Register
237
B1.61 Hyp Configuration Register
240
B1.62 Hyp Configuration Register 2
246
B1.63 Hyp Debug Control Register
248
B1.64 Hyp Data Fault Address Register
251
B1.65 Hyp Instruction Fault Address Register
252
B1.66 Hyp IPA Fault Address Register
253
B1.67 Hyp System Control Register
254
B1.68 Hyp Syndrome Register
258
B1.69 Hyp System Trap Register
259
B1.70 Hyp Translation Control Register
263
B1.71 Hyp Vector Base Address Register
265
B1.72 Auxiliary Feature Register 0
266
B1.73 Debug Feature Register 0
267
B1.74 Instruction Set Attribute Register 0
269
B1.75 Instruction Set Attribute Register 1
271
B1.76 Instruction Set Attribute Register 2
273
B1.77 Instruction Set Attribute Register 3
275
B1.78 Instruction Set Attribute Register 4
277
B1.79 Instruction Set Attribute Register 5
279
B1.80 Memory Model Feature Register 0
281
B1.81 Memory Model Feature Register 1
283
B1.82 Memory Model Feature Register 2
285
B1.83 Memory Model Feature Register 3
287
B1.84 Processor Feature Register 0
289
B1.85 Processor Feature Register 1
291
B1.86 Instruction Fault Address Register
293
B1.87 Instruction Fault Status Register
294
B1.88 IFSR with Short-Descriptor Translation Table Format
295
B1.89 IFSR with Long-Descriptor Translation Table Format
297
B1.90 Interrupt Status Register
299
B1.91 L2 Auxiliary Control Register
301
B1.92 L2 Control Register
303
B1.93 L2 Extended Control Register
305
B1.94 L2 Memory Error Syndrome Register
307
B1.95 Memory Attribute Indirection Registers 0 and 1
310
B1.96 Main ID Register
313
B1.97 Multiprocessor Affinity Register
315
B1.98 Non-Secure Access Control Register
317
B1.99 Normal Memory Remap Register
319
B1.100 Physical Address Register
321
B1.101 Primary Region Remap Register
322
B1.102 Revision ID Register
325
B1.103 Reset Management Register
326
B1.104 Secure Configuration Register
328
B2.92 System Control Register, EL3
328
B1.105 System Control Register
331
B1.106 Secure Debug Control Register
335
B1.107 Secure Debug Enable Register
337
B1.108 TCM Type Register
339
B1.109 TLB Type Register
340
B1.110 Translation Table Base Control Register
341
B1.111 TTBCR with Short-Descriptor Translation Table Format
342
B1.112 TTBCR with Long-Descriptor Translation Table Format
343
B1.113 Translation Table Base Register 0
346
B1.114 TTBR0 with Short-Descriptor Translation Table Format
347
B1.115 TTBR0 with Long-Descriptor Translation Table Format
349
B1.116 Translation Table Base Register 1
350
B1.117 TTBR1 with Short-Descriptor Translation Table Format
351
B1.118 TTBR1 with Long-Descriptor Translation Table Format
353
B1.119 Vector Base Address Register
354
B1.120 Virtualization Multiprocessor ID Register
355
B1.121 Virtualization Processor ID Register
356
B1.122 Virtualization Translation Control Register
357
B2.1 Aarch64 Register Summary
362
B2.2 Aarch64 Identification Registers
363
B2.3 Aarch64 Exception Handling Registers
365
B2.4 Aarch64 Virtual Memory Control Registers
366
B2.5 Aarch64 Other System Control Registers
368
B2.6 Aarch64 Cache Maintenance Operations
369
B2.7 Aarch64 TLB Maintenance Operations
370
B2.8 Aarch64 Address Translation Operations
371
B2.9 Aarch64 Miscellaneous Operations
372
B2.10 Aarch64 Performance Monitor Registers
373
B2.11 Aarch64 Reset Registers
375
B2.12 Aarch64 Secure Registers
376
B2.13 Aarch64 Virtualization Registers
377
B2.14 Aarch64 EL2 TLB Maintenance Operations
379
B2.15 Aarch64 GIC System Registers
380
B2.16 Aarch64 Generic Timer Registers
382
B2.17 Aarch64 Thread Registers
383
B2.18 Aarch64 Implementation Defined Registers
384
B2.19 Auxiliary Control Register, EL1
386
B2.20 Auxiliary Control Register, EL2
387
B2.21 Auxiliary Control Register, EL3
389
B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3
391
B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3
392
B2.24 Auxiliary ID Register, EL1
393
B2.25 Auxiliary Memory Attribute Indirection Register, EL1
394
B2.26 Auxiliary Memory Attribute Indirection Register, EL2
395
B2.27 Auxiliary Memory Attribute Indirection Register, EL3
396
B2.28 Configuration Base Address Register, EL1
397
B2.29 Cache Size ID Register, EL1
398
B2.30 Cache Level ID Register, EL1
400
B2.31 Architectural Feature Access Control Register, EL1
402
B2.32 Architectural Feature Trap Register, EL2
404
B2.33 Architectural Feature Trap Register, EL3
406
B2.34 Cache Size Selection Register, EL1
408
B2.35 Cache Type Register, EL0
410
B2.36 CPU Auxiliary Control Register, EL1
412
B2.37 CPU Extended Control Register, EL1
416
B2.38 CPU Memory Error Syndrome Register, EL1
418
B2.39 Domain Access Control Register, EL2
421
B2.40 Data Cache Zero ID Register, EL0
422
B2.41 Exception Syndrome Register, EL1
423
B2.42 Exception Syndrome Register, EL2
425
B2.43 Exception Syndrome Register, EL3
427
B2.44 Fault Address Register, EL1
429
B2.45 Fault Address Register, EL2
430
B2.46 Fault Address Register, EL3
431
B2.47 Hyp Auxiliary Configuration Register, EL2
432
B2.48 Hypervisor Configuration Register, EL2
433
B2.49 Hypervisor IPA Fault Address Register, EL2
440
B2.50 Hyp System Trap Register, EL2
441
B2.51 Aarch64 Debug Feature Register 0, EL1
444
B2.52 Aarch64 Instruction Set Attribute Register 0, EL1
446
B2.53 Aarch64 Memory Model Feature Register 0, EL1
448
B2.54 Aarch64 Processor Feature Register 0, EL1
450
B2.55 Aarch32 Auxiliary Feature Register 0, EL1
452
B2.56 Aarch32 Debug Feature Register 0, EL1
453
B2.57 Aarch32 Instruction Set Attribute Register 0, EL1
455
B2.58 Aarch32 Instruction Set Attribute Register 1, EL1
457
B2.59 Aarch32 Instruction Set Attribute Register 2, EL1
459
B2.60 Aarch32 Instruction Set Attribute Register 3, EL1
461
B2.61 Aarch32 Instruction Set Attribute Register 4, EL1
463
B2.62 Aarch32 Instruction Set Attribute Register 5, EL1
465
B2.63 Aarch32 Memory Model Feature Register 0, EL1
467
B2.64 Aarch32 Memory Model Feature Register 1, EL1
469
B2.65 Aarch32 Memory Model Feature Register 2, EL1
471
B2.66 Aarch32 Memory Model Feature Register 3, EL1
473
B2.67 Aarch32 Processor Feature Register 0, EL1
475
B2.68 Aarch32 Processor Feature Register 1, EL1
477
B2.69 Instruction Fault Status Register, EL2
479
B2.70 IFSR32_EL2 with Short-Descriptor Translation Table Format
480
B2.71 IFSR32_EL2 with Long-Descriptor Translation Table Format
482
B2.72 Interrupt Status Register, EL1
484
B2.73 L2 Auxiliary Control Register, EL1
486
B2.74 L2 Control Register, EL1
489
B2.75 L2 Extended Control Register, EL1
491
B2.76 L2 Memory Error Syndrome Register, EL1
493
B2.77 Memory Attribute Indirection Register, EL1
496
B2.78 Memory Attribute Indirection Register, EL2
498
B2.79 Memory Attribute Indirection Register, EL3
499
B2.80 Monitor Debug Configuration Register, EL2
500
B2.81 Monitor Debug Configuration Register, EL3
503
B2.82 Monitor Debug System Control Register, EL1
506
B2.83 Main ID Register, EL1
510
B2.84 Multiprocessor Affinity Register, EL1
512
B2.85 Physical Address Register, EL1
514
B2.86 Revision ID Register, EL1
518
B2.87 Reset Management Register, EL3
519
B2.88 Reset Vector Base Address Register, EL3
521
B2.89 Secure Configuration Register, EL3
522
B2.90 System Control Register, EL1
525
B2.91 System Control Register, EL2
529
B2.93 Secure Debug Enable Register, EL3
535
B2.94 Translation Control Register, EL1
536
B2.95 Translation Control Register, EL2
540
Translation Control Register, EL3
540
B2.96 Translation Control Register, EL3
543
B2.97 Translation Table Base Register 0, EL1
546
B2.98 Translation Table Base Register 1, EL1
548
B2.99 Translation Table Base Register 0, EL3
550
B2.100 Vector Base Address Register, EL1
551
B2.101 Vector Base Address Register, EL2
552
B2.102 Vector Base Address Register, EL3
553
B2.103 Virtualization Multiprocessor ID Register, EL2
554
B2.104 Virtualization Processor ID Register, EL2
555
B2.105 Virtualization Translation Control Register, EL2
556
Chapter B3
559
GIC Registers
559
B3.1 CPU Interface Register Summary
560
B3.2 Active Priority Register
561
B3.3 CPU Interface Identification Register
562
B3.4 Virtual Interface Control Register Summary
563
B3.5 VGIC Type Register
564
B3.6 Virtual CPU Interface Register Summary
565
B3.7 VM Active Priority Register
566
B3.8 VM CPU Interface Identification Register
567
Chapter B4
569
Generic Timer Registers
569
B4.1 Generic Timer Register Summary
570
B4.2 Aarch32 Generic Timer Register Summary
571
B4.3 Aarch64 Generic Timer Register Summary
572
Debug
573
Part C
573
Chapter C1
575
Debug
575
C1.1 about Debug Methods
576
C1.2 Debug Access
577
C1.3 Effects of Resets on Debug Registers
578
C1.4 External Access Permissions to Debug Registers
579
C1.5 Debug Events
580
C1.6 Debug Memory Map
581
C1.7 Debug Signals
583
C1.8 Changing the Authentication Signals for Debug
584
Chapter C2
585
Pmu
585
C2.1 about the PMU
586
C2.2 External Register Access Permissions to the PMU Registers
587
C2.3 Performance Monitoring Events
588
C2.4 PMU Interrupts
592
C2.5 Exporting PMU Events
593
C3.1 about the ETM
596
C3.2 Configuration Options for the ETM Unit and Trace Resources
598
C3.3 Resetting the ETM
600
C3.4 Programming and Reading ETM Trace Unit Registers
601
C5.1 about Direct Access to Internal Memory
608
C5.2 Encoding for Tag and Data in the L1 Instruction Cache
609
C5.3 Encoding for Tag and Data in the L1 Data Cache
610
C5.4 Encoding for the Main TLB RAM
612
C5.5 Encoding for Walk Cache
617
C5.6 Encoding for IPA Cache
618
C6.1 Aarch32 Debug Register Summary
620
C6.2 Debug Breakpoint Control Registers
622
C6.3 Debug Watchpoint Control Registers
625
C6.4 Debug ID Register
628
C6.5 Debug Device ID Register
630
C6.6 Debug Device ID Register 1
632
C7.1 Aarch64 Debug Register Summary
633
C7.2 Debug Breakpoint Control Registers, EL1
635
C8.1 Memory-Mapped Debug Register Summary
644
C8.2 External Debug Reserve Control Register
648
C8.3 External Debug Integration Mode Control Register
650
C8.4 External Debug Device ID Register 0
651
C8.5 External Debug Device ID Register 1
652
C8.6 External Debug Processor Feature Register
653
C8.7 External Debug Feature Register
655
C8.8 External Debug Peripheral Identification Registers
657
C8.9 External Debug Peripheral Identification Register 0
658
C8.10 External Debug Peripheral Identification Register 1
659
C8.11 External Debug Peripheral Identification Register 2
660
C8.12 External Debug Peripheral Identification Register 3
661
C8.13 External Debug Peripheral Identification Register 4
662
C8.14 External Debug Peripheral Identification Register 5-7
663
C8.15 External Debug Component Identification Registers
664
C8.16 External Debug Component Identification Register 0
665
C8.17 External Debug Component Identification Register 1
666
C8.18 External Debug Component Identification Register 2
667
C8.19 External Debug Component Identification Register 3
668
Chapter C9 ROM Table
669
C9.1 about the ROM Table
670
C9.2 ROM Table Register Interface
671
C9.3 ROM Table Register Summary
672
C9.4 ROM Entry Registers
673
C9.5 ROM Table Peripheral Identification Registers
677
C9.6 ROM Table Peripheral Identification Register 0
678
C9.7 ROM Table Peripheral Identification Register 1
679
C9.8 ROM Table Peripheral Identification Register 2
680
C9.9 ROM Table Peripheral Identification Register 3
681
C9.10 ROM Table Peripheral Identification Register 4
682
C9.11 ROM Table Peripheral Identification Register 5-7
683
C9.12 ROM Table Component Identification Registers
684
C9.13 ROM Table Component Identification Register 0
685
C9.14 ROM Table Component Identification Register 1
686
C9.15 ROM Table Component Identification Register 2
687
C9.16 ROM Table Component Identification Register 3
688
C10.1 Aarch32 PMU Register Summary
690
C10.2 Performance Monitors Control Register
692
C10.3 Performance Monitors Common Event Identification Register 0
695
C10.4 Performance Monitors Common Event Identification Register 1
699
C10.5 Aarch64 PMU Register Summary
702
C10.6 Performance Monitors Control Register, EL0
704
C10.7 Performance Monitors Common Event Identification Register 0, EL0
707
C10.8 Performance Monitors Common Event Identification Register 1, EL0
711
C10.9 Memory-Mapped PMU Register Summary
714
C10.10 Performance Monitors Configuration Register
717
C10.11 Performance Monitors Peripheral Identification Registers
719
C10.12 Performance Monitors Peripheral Identification Register 0
720
C10.13 Performance Monitors Peripheral Identification Register 1
721
C10.14 Performance Monitors Peripheral Identification Register 2
722
C10.15 Performance Monitors Peripheral Identification Register 3
723
C10.16 Performance Monitors Peripheral Identification Register 4
724
C10.17 Performance Monitors Peripheral Identification Register 5-7
725
C10.18 Performance Monitors Component Identification Registers
726
C10.19 Performance Monitors Component Identification Register 0
727
C10.20 Performance Monitors Component Identification Register 1
728
C10.21 Performance Monitors Component Identification Register 2
729
C10.22 Performance Monitors Component Identification Register 3
730
C11.1 ETM Register Summary
733
C11.2 Programming Control Register
736
C11.3 Status Register
737
C11.4 Trace Configuration Register
738
C11.5 Branch Broadcast Control Register
740
C11.6 Auxiliary Control Register
741
C11.7 Event Control 0 Register
743
C11.8 Event Control 1 Register
745
C11.9 Stall Control Register
746
C11.10 Global Timestamp Control Register
747
C11.11 Synchronization Period Register
748
C11.12 Cycle Count Control Register
749
C11.13 Trace ID Register
750
C11.14 Viewinst Main Control Register
751
C11.15 Viewinst Include-Exclude Control Register
753
C11.16 Viewinst Start-Stop Control Register
754
C11.17 Sequencer State Transition Control Registers 0-2
755
C11.18 Sequencer Reset Control Register
757
C11.19 Sequencer State Register
758
C11.20 External Input Select Register
759
C11.21 Counter Reload Value Registers 0-1
760
C11.22 Counter Control Register 0
761
C11.23 Counter Control Register 1
763
C11.24 Counter Value Registers 0-1
765
C11.25 ID Register 8
766
C11.26 ID Register 9
767
C11.27 ID Register 10
768
C11.28 ID Register 11
769
C11.29 ID Register 12
770
C11.30 ID Register 13
771
C11.31 Implementation Specific Register 0
772
C11.32 ID Register 0
773
C11.33 ID Register 1
775
C11.34 ID Register 2
776
C11.35 ID Register 3
778
C11.36 ID Register 4
780
C11.37 ID Register 5
782
C11.38 Resource Selection Control Registers 2-16
784
C11.39 Single-Shot Comparator Control Register 0
785
C11.40 Single-Shot Comparator Status Register 0
786
C11.41 os Lock Access Register
787
C11.42 os Lock Status Register
788
C11.43 Power down Control Register
789
C11.44 Power down Status Register
790
C11.45 Address Comparator Value Registers 0-7
791
C11.46 Address Comparator Access Type Registers 0-7
792
C11.47 Context ID Comparator Value Register 0
794
C11.48 VMID Comparator Value Register 0
795
C11.49 Context ID Comparator Control Register 0
796
C11.50 Integration ATB Identification Register
797
C11.51 Integration Instruction ATB Data Register
798
C11.52 Integration Instruction ATB in Register
799
C11.53 Integration Instruction ATB out Register
800
C11.54 Integration Mode Control Register
801
C11.55 Claim Tag Set Register
802
C11.56 Claim Tag Clear Register
803
C11.57 Device Affinity Register 0
804
C11.58 Device Affinity Register 1
806
C11.59 Software Lock Access Register
807
C11.60 Software Lock Status Register
808
C11.61 Authentication Status Register
809
C11.62 Device Architecture Register
810
C11.63 Device ID Register
811
C11.64 Device Type Register
812
C11.65 ETM Peripheral Identification Registers
813
C11.66 ETM Peripheral Identification Register 0
814
C11.67 ETM Peripheral Identification Register 1
815
C11.68 ETM Peripheral Identification Register 2
816
C11.69 ETM Peripheral Identification Register 3
817
C11.70 ETM Peripheral Identification Register 4
818
C11.71 ETM Peripheral Identification Register 5-7
819
C11.72 ETM Component Identification Registers
820
C11.73 ETM Component Identification Register 0
821
C11.74 ETM Component Identification Register 1
822
C11.75 ETM Component Identification Register 2
823
C11.76 ETM Component Identification Register 3
824
C12.1 Cross Trigger Register Summary
826
C12.2 External Register Access Permissions to the CTI Registers
828
C12.3 CTI Device Identification Register
829
C12.4 CTI Integration Mode Control Register
831
C12.5 CTI Peripheral Identification Registers
832
C12.6 CTI Peripheral Identification Register 0
833
C12.7 CTI Peripheral Identification Register 1
834
C12.8 CTI Peripheral Identification Register 2
835
C12.9 CTI Peripheral Identification Register 3
836
C12.10 CTI Peripheral Identification Register 4
837
C12.11 CTI Peripheral Identification Register 5-7
838
C12.12 CTI Component Identification Registers
839
C12.13 CTI Component Identification Register 0
840
C12.14 CTI Component Identification Register 1
841
C12.15 CTI Component Identification Register 2
842
C12.16 CTI Component Identification Register 3
843
A.8 L2 Error Signals
858
A.9 ACP Interface Signals
859
A.10 Broadcast Signals for the Memory Interface
861
A.11 AXI Interface Signals
862
A.12 ACE Interface Signals
864
A.13 CHI Interface Signals
868
A.14 Debug Signals
871
A.15 APB Interface Signals
873
A.16 ATB Interface Signals
874
A.17 ETM Signals
875
A.18 PMU Interface Signals
876
A.19 CTI Interface Signals
877
A.20 DFT Interface Signals
878
A.21 MBIST Interface Signals
879
B.1 Use of R15 by Instruction
882
B.2 UNPREDICTABLE Instructions Within an IT Block
883
B.3 Load/Store Accesses Crossing Page Boundaries
884
B.4 Armv8 Debug UNPREDICTABLE Behaviors
885
B.5 Other UNPREDICTABLE Behaviors
889
C.1 Revisions
892
4
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ARM Cortex-A35 Specifications
General
Brand
ARM
Model
Cortex-A35
Category
Computer Hardware
Language
English
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