B1.111 TTBCR with Short-descriptor translation table format
TTBCR has a specific format when using the Short-descriptor translation table format. TTBCR.EAE
determines which format of the register is in use.
The following figure shows the TTBCR bit assignments when TTBCR.EAE is 0.
31 30 6 5 4 3 2
0
NRES0
PD1EAE
PD0
RES0
Figure B1-61 TTBCR bit assignments, TTBCR.EAE is 0
EAE, [31]
Extended Address Enable.
0 Use the 32-bit translation system, with the Short-descriptor translation table format.
[30:6]
Reserved, RES0.
PD1, [5]
Translation table walk disable for translations using TTBR1. This bit controls whether a
translation table walk is performed on a TLB miss, for an address that is translated using
TTBR1. The possible values are:
0 Perform translation table walks using TTBR1.
1
A TLB miss on an address that is translated using TTBR1 generates a Translation fault.
No translation table walk is performed.
PD0, [4]
Translation table walk disable for translations using TTBR0. This bit controls whether a
translation table walk is performed on a TLB miss for an address that is translated using
TTBR0. The possible values are:
0 Perform translation table walks using TTBR0.
1
A TLB miss on an address that is translated using TTBR0 generates a Translation fault.
No translation table walk is performed.
[3]
Reserved, RES0.
N, [2:0]
Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is
bits[31:14-N]. The value of N also determines:
• Whether TTBR0 or TTBR1 is used as the base address for translation table walks.
• The size of the translation table pointed to by TTBR0.
N can take any value from 0 to 7, that is, from 0b000 to 0b111.
When N has its reset value of 0, the translation table base is compatible with Armv5 and Armv6.
Resets to 0.
B1 AArch32 system registers
B1.111 TTBCR with Short-descriptor translation table format
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-342
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