B1.64 Hyp Data Fault Address Register
The HDFAR characteristics are:
Purpose
Holds the virtual address of the faulting address that caused a synchronous Data Abort exception
that is taken to Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
- - - RW RW -
An execution in a Non-secure EL1 state, or in Secure state, makes the HDFAR UNKNOWN.
Configurations
HDFAR is architecturally mapped to AArch64 register FAR_EL2[31:0] when EL3 is AArch64.
See B2.45 Fault Address Register, EL2 on page B2-430.
HDFAR (S) is architecturally mapped to AArch32 register DFAR (S). See B1.48 Data Fault
Address Register on page B1-222.
Attributes
HDFAR is a 32-bit register.
31
0
VA of faulting address of synchronous Data Abort exception
Figure B1-20 HDFAR bit assignments
VA, [31:0]
The Virtual Address of faulting address of synchronous Data Abort exception.
To access the HDFAR:
MRC p15, 4, <Rt>, c6, c0, 0 ; Read HDFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 0 ; Write Rt to HDFAR
Register access is encoded as follows:
Table B1-49 HDFAR access encoding
coproc opc1 CRn CRm opc2
1111 100 0110 0000 000
B1 AArch32 system registers
B1.64 Hyp Data Fault Address Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-251
Non-Confidential
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