ARM Cortex-A35 User Manual

B2.34 Cache Size Selection Register, EL1
CSSELR_EL1
The CSSELR_EL1 characteristics are:
Purpose
Selects the current B1.39 Cache Size ID Register on page B1-201, by specifying:
• The required cache level.
• The cache type, either instruction or data cache.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
CSSELR_EL1 is architecturally mapped to AArch32 register CSSELR(NS). See B1.45 Cache
Size Selection Register on page B1-217.
Attributes
CSSELR_EL1 is a 32-bit register.
InD
UNK/SBZP
31 4 3 1 0
Level
Figure B2-9 CSSELR_EL1 bit assignments
[31:4]
Reserved, RES0.
Level, [3:1]
Cache level of required cache:
0b000 L1.
0b001 L2.
0b010-0b111 Reserved.
The combination of Level=0b001 and InD=1 is reserved.
InD, [0]
Instruction not Data bit:
0 Data or unified cache.
1 Instruction cache.
The combination of Level=0b001 and InD=1 is reserved.
To access the CSSELR_EL1:
MRS <Xt>, CSSELR_EL1 ; Read CSSELR_EL1 into Xt
MSR CSSELR_EL1, <Xt> ; Write Xt to CSSELR_EL1
B2 AArch64 system registers
B2.34 Cache Size Selection Register, EL1
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reserved.
B2-408
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English