B1.71 Hyp Vector Base Address Register
The HVBAR characteristics are:
Purpose
Holds the exception base address for any exception that is taken to Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
The HVBAR is architecturally mapped to the AArch64 VBAR_EL2[31:0]. See B2.101 Vector
Base Address Register, EL2 on page B2-552.
Attributes
HVBAR is a 32-bit register.
RES0
31
0
Vector Base Address
45
Figure B1-27 HVBAR bit assignments
Vector Base Address, [31:5]
Bits[31:5] of the base address of the exception vectors, for exceptions taken in this exception
level. Bits[4:0] of an exception vector are the exception offset.
[4:0]
Reserved, RES0.
To access the HVBAR:
MRC p15, 4, <Rt>, c12, c0, 0 ; Read HVBAR into Rt
MCR p15, 4, <Rt>, c12, c0, 0 ; Write Rt to HVBAR
Register access is encoded as follows:
Table B1-55 HVBAR access encoding
coproc opc1 CRn CRm opc2
1111 100 1100 0000 000
B1 AArch32 system registers
B1.71 Hyp Vector Base Address Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-265
Non-Confidential
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