B2.49 Hypervisor IPA Fault Address Register, EL2
The HPFAR_EL2 characteristics are:
Purpose
Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
HPFAR_EL2[31:0] is mapped to AArch32 register HPFAR. See B1.66 Hyp IPA Fault Address
Register on page B1-253.
Attributes
HPFAR_EL2 is a 64-bit register.
3940 063
FIPA[47:12]RES0
34
RES0
Figure B2-23 HPFAR_EL2 bit assignments
[63:40]
Reserved, RES0.
FIPA[47:12], [39:4]
Bits [47:12] of the faulting intermediate physical address. The equivalent upper bits in this field
are RES0.
[3:0]
Reserved, RES0.
To access the HPFAR_EL:
MRS <Xt>, HPFAR_EL2 ; Read EL2 Fault Address Register
MSR HPFAR_EL2, <Xt> ; Write EL2 Fault Address Register
Register access is encoded as follows:
Table B2-42 HPFR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 0110 0000 100
B2 AArch64 system registers
B2.49 Hypervisor IPA Fault Address Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-440
Non-Confidential
To Next Page
Loading...
Need help?
General
