B1.106 Secure Debug Control Register
The SDCR characteristics are:
Purpose
Controls debug and performance monitors functionality in Secure state.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW - RW RW
Configurations
SDCR is mapped to AArch64 register MDCR_EL3. See B2.81 Monitor Debug Configuration
Register, EL3 on page B2-503.
If EL3 is using AArch32, write access to SDCR is disabled when the CP15SDISABLE2 signal
is asserted HIGH.
Attributes
SDCR is a 32-bit register.
31 14 13 0
1821 20 19
EPMAD SPD
17 16 15
RES0
RES0
SPME
EDAD
22
RES0RES0
Figure B1-59 SDCR bit assignments
[31:22]
Reserved, RES0.
EPMAD, [21]
External debugger access to Performance Monitors registers disabled. This disables access to
these registers by an external debugger:
0 Access to Performance Monitors registers from external debugger is permitted. This is the
reset value.
1 Access to Performance Monitors registers from external debugger is disabled, unless
overridden by authentication interface.
EDAD, [20]
External debugger access to breakpoint and watchpoint registers disabled. This disables access
to these registers by an external debugger:
0 Access to breakpoint and watchpoint registers from external debugger is permitted. This is
the reset value.
1 Access to breakpoint and watchpoint registers from external debugger is disabled, unless
overridden by authentication interface.
[19:18]
Reserved, RES0.
B1 AArch32 system registers
B1.106 Secure Debug Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-335
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